Discrete-time signal processing
Discrete-time signal processing
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Power scalable processing using distributed arithmetic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Low-power filtering via adaptive error-cancellation
IEEE Transactions on Signal Processing
IEEE Communications Magazine
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient motion estimation using error-tolerance
Proceedings of the 2006 international symposium on Low power electronics and design
On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power robust signal processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
On improving the algorithmic robustness of a low-power FIR filter
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computation error analysis in digital signal processing systems with overscaled supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Computation as estimation: a general framework for robustness and energy efficiency in SoCs
IEEE Transactions on Signal Processing
Efficient soft error-tolerant adaptive equalizers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Scalable stochastic processors
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing energy to minimize errors in dataflow graphs using approximate adders
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Stochastic networked computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process-variation resilient and voltage scalable DCT architecture for robust low-power computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IMPACT: imprecise adders for low-power approximate computing
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Significance driven computation on next-generation unreliable platforms
Proceedings of the 48th Design Automation Conference
Error-resilient low-power DSP via path-delay shaping
Proceedings of the 48th Design Automation Conference
Reduced-precision redundancy on FPGAs
International Journal of Reconfigurable Computing
A methodology for energy-quality tradeoff using imprecise hardware
Proceedings of the 49th Annual Design Automation Conference
Journal of Signal Processing Systems
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Proceedings of the 7th International Conference on Body Area Networks
An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% energy savings with no loss in the signal-to-noise ratio (SNR) for receive filtering in a QPSK system and the butterfly of fast Fourier transform (FFT) in a WLAN OFDM system, respectively. These energy savings are with respect to optimally scaled (i.e., the supply voltage equals the critical voltage Vdd-crit) present day systems. Further, we show that the RPR technique is able to maintain the output SNR for error rates of up to 0.09/sample and 0.06/sample in an finite impulse response filter and a FFT block, respectively.