Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

Authors:
Georgios Karakonstantis;Debabrata Mohapatra;Kaushik Roy
Affiliations:
Electrical Engineering, Telecommunications Circuits Lab, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland 1015;ECE School, Purdue University, West Lafayette, USA 47907;ECE School, Purdue University, West Lafayette, USA 47907
Venue:
Journal of Signal Processing Systems
Year:
2012

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Abstract

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less- crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system---logic and memory---and spans multiple layers of design hierarchy---algorithm, architecture and circuit. The design methodology when applied to a multimedia sub-system shows large power benefits (up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.