Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency
Proceedings of the 47th Design Automation Conference
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We propose a low-power filtering algorithm developed via the soft DSP framework. Soft DSP refers to scaling the supply voltage of a DSP implementation beyond the voltage required to match its critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is then compensated for via algorithmic error-control schemes. The proposed error-control schemes, based on forward/backward linear prediction, provides improved performance over the ones proposed in the past by exploiting correlation in both leading and trailing samples with a latency penalty. It is shown that (a) the proposed scheme provides 60-80% reduction in energy dissipation over that achieved via conventional voltage scaling and (b) for the same algorithmic performance, the overhead involved in the proposed algorithm is more than 50% smaller than existing schemes for medium bandwidth filters.