Communications of the ACM
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Specification, synthesis, and verification of hazard-free asynchronous circuits
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Self-timed data transmission in massively parallel computing systems
Integrated Computer-Aided Engineering
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
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The goal of this research is to enable the actual building of parallel machines. The example chosen in this paper isa heterogeneous parallel machine with an intrinsic asynchronous behavior. An asynchronous router fully supports such a logical asynchronism.However, every parallel processor would exhibit asynchronism similar enough to warrant the study of a general methodology. The main part of the paper deals with an original method that ensures a hazard-free self-timed design assuming the worst conditions for robustness.Hazards are classified under three types. On top of logic hazards that resort to implementation, equation hazards are eliminatedby an optimal covering. A new variable labelled state-trajectory is proposed: its integrity guarantees immunity to function hazards. The method was fruitfully applied to the VLSI CMOS implementation of the above-mentioned router. Peculiar fully customized cells were designed. Circuit-measured performances as well as some machine inner-communication performances are presented.