The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Low-Cost Online Testing of Asynchronous Handshakes
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Wide VDDembedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Self-timed SRAM for energy harvesting systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
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The most efficient power saving method in digital systems is to scale Vdd, owing to the quadratic dependence of dynamic power consumption. This requires memory working under a wide range of Vdds in terms of performance and power saving requirements. A self-timed 6T SRAM was previously proposed, which adapts to the variable Vdd automatically. However due to leakage, the size of memory is restricted by process variations. This paper reports a new self-timed 10T SRAM cell with bit line keepers developed to improve robustness in order to work in a wide range of Vdds down to 0.3V under PVT variations. In addition, this paper briefly discusses the potential benefits of the self-timed SRAM for designing highly reliable systems and detecting the data retention voltage (DRV).