Self-timed SRAM for energy harvesting systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Improving the robustness of self-timed SRAM to variable Vdds
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
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This paper details the design of 1GHz pipelined asynchronous SRAMs in TSMC's 65nm GP process. We show how targeted timing assumptions improve an otherwise quasi delay-insensitive (QDI) design. The speed, area, and power of our SRAMs are compared to commercially available synchronous SRAMs in the same technology. We also present novel techniques for implementing large pseudo dual-ported memories that support simultaneous reads and writes. The most sophisticated of three designs yields a fully provisioned dual-ported memory using multiple single-ported banks connected by dual-ported buses, plus a small side-band memory to avoid bank conflicts. We discuss our solutions for manufacturing defects, soft-errors, and analog robustness with attention to advantages and challenges of our asynchronous methodology. Laboratory measurements of a test-chip demonstrate correct functionality at speeds well over a GHz. Our single-ported SRAM designs are larger but faster than the alternate synchronous designs, while our novel dual-ported implementations can be both smaller and much faster. These technology advantages lead directly to competitive advantages for our future commercial products.