Communicating sequential processes
Communicating sequential processes
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Acta Informatica
A unified signal transition graph model for asynchronous control circuit synthesis
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
A Fundamental Tehoerem of Asynchronous Parallel Computation
Proceedings of the Sagamore Computer Conference on Parallel Processing
Optimised state assignment for asynchronous circuit synthesis
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Sequencer circuits for VLSI programming
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Concurrency and Hardware Design, Advances in Petri Nets
An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
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Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements manifest themselves as global properties of circuits, properties that may be incompatible with the specification to be implemented. This paper investigates several such properties (concerned with persistence, commutativity and inertia) by means of a formal analysis carried out using Josephs' Receptive Process Theory.