Communicating sequential processes
Communicating sequential processes
Communication and concurrency
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Acta Informatica
Correct compilation of specifications to deterministic asynchronous circuits
Formal Methods in System Design
The Design and Use of Hazard-Free Switching Networks
Journal of the ACM (JACM)
A Fundamental Tehoerem of Asynchronous Parallel Computation
Proceedings of the Sagamore Computer Conference on Parallel Processing
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Some Limitations to Speed-Independence in Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Analyzing Specifications for Delay-Insensitive Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
SHIM: a deterministic model for heterogeneous embedded systems
Proceedings of the 5th ACM international conference on Embedded software
On Process-algebraic Verification of Asynchronous Circuits
Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
SHIM: a deterministic model for heterogeneous embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
On Process-algebraic Verification of Asynchronous Circuits
Fundamenta Informaticae - Half a Century of Inspirational Research: Honoring the Scientific Influence of Antoni Mazurkiewicz
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Receptive process theory provides a semantic model for reasoning aboutnput/output-systems in general, and about the switching behaviour of asynchronous circuits in particular. As in the failures/divergences model of Hoare's CSP, nondeterministic behaviour, as might result from the use of arbiters and synchronizers, can be modelled. A new result is the identification of the class of deterministic receptive processes, which is closed under composition. The defining characteristic of the class is that the behaviour of its members can be adequately described using a traces/divergences model. The closure of the class is proved with respect to a binary, parallel composition operator which allows inputs to be forked isochronically to both components and which conceals those outputs of either component that are inputs to the other component. This result contrasts with CSP, in which determinacy is not preserved when events are concealed.