Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Modeling concurrency with partial orders
International Journal of Parallel Programming
A general state graph transformation framework for asynchronous synthesis
EURO-DAC '94 Proceedings of the conference on European design automation
What is the cost of delay insensitivity?
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An Improvement of McMillan's Unfolding Algorithm
Formal Methods in System Design
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of concurrency to system design
Analyzing Specifications for Delay-Insensitive Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Towards Asynchronous A-D Conversion
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
State encoding of large asynchronous controllers
Proceedings of the 43rd annual Design Automation Conference
Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Behaviour-preserving transition insertions in unfolding prefixes
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Efficient automatic resolution of encoding conflicts using STG unfoldings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A combined framework for the resolution of encoding conflicts in STG unfoldings is presented, which extends previouswork by incorporating concurrency reduction in addition to signal insertion. Furthermore, a novel validity condition is proposed to justify these transformations. The method has been implemented in the CONFRES tool and applied to a number of case studies. The experimental results show that the combined framework enlarges the design space and allows for better exploration of the speed/area tradeoff.