The complexity of Boolean functions
The complexity of Boolean functions
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
A general state graph transformation framework for asynchronous synthesis
EURO-DAC '94 Proceedings of the conference on European design automation
An Improvement of McMillan's Unfolding Algorithm
Formal Methods in System Design
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of concurrency to system design
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Lectures on Petri Nets I: Basic Models, Advances in Petri Nets, the volumes are based on the Advanced Course on Petri Nets
Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
On the Complexity of Consistency and Complete State Coding for Signal Transition Graphs
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Behaviour-preserving transition insertions in unfolding prefixes
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Combining decomposition and unfolding for STG synthesis
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Synthesis of asynchronous controllers using integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Encoding Large Asynchronous Controllers With ILP Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new type of behaviour-preserving transition insertions in unfolding prefixes
ICGT'10 Proceedings of the 5th international conference on Graph transformations
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Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. In this paper, a fully automatic technique for resolving such conflicts by means of insertion of new signals and concurrency reduction is proposed. It is based on conflict cores, i.e., sets of transitions causing encoding conflicts, which are represented at the level of finite and complete unfolding prefixes, and a SAT solver is used to find where in the STG the transitions of new signals should be inserted and to check the validity of concurrency reductions. The experimental results show significant improvements over the state space based approach in terms of runtime and memory consumption, as well as some improvements in the quality of the resulting circuits.