What is the cost of delay insensitivity?
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Influence of Metastability Errors on SNR in Successive-Approximation A/D Converters
Analog Integrated Circuits and Signal Processing
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Formal Asynchronous Systems Modelling
Fundamenta Informaticae
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Analog to digital (A-D) converters with a fixed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time for decisions, and are potentially severe. We estimate the frequency of these errors in a successive approximation converter, and compare the results with asynchronous designs using both a fully speed-independent, and a bundled data approach. It is shown that an asynchronous converter is more reliable than its synchronous counterpart, and that the bundled data design is also faster, on average, than the synchronous design. We also demonstrate tradeoffs involved in asynchronous converter designs, such as speed, robustness to delay variations, circuit size and design scalability.