Reachability in cyclic extended free-choice systems
Selected papers of the 3rd workshop on Concurrency and compositionality
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Symbolic hazard-free minimization and encoding of asynchronous finite state machines
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Lectures on Petri Nets I: Basic Models, Advances in Petri Nets, the volumes are based on the Advanced Course on Petri Nets
Detecting State Coding Conflicts in STG Unfoldings Using SAT
ACSD '03 Proceedings of the Third International Conference on Application of Concurrency to System Design
A Burst-Mode Oriented Back-End for the Balsa Synthesis System
Proceedings of the conference on Design, automation and test in Europe
ILP Models for the Synthesis of Asynchronous Control Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A region-based theory for state assignment in speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Output-Determinacy and Asynchronous Circuit Synthesis
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Combining decomposition and unfolding for STG synthesis
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Output-Determinacy and Asynchronous Circuit Synthesis
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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A novel method to solve the state encoding problem in Signal Transition Graphs is presented. It is based on the structural theory of Petri nets and can be applied to large specifications with hundreds of signals. This new method opens the door to incorporate logic synthesis in the design flow of large control circuits obtained from high-level specifications. The experimental results validate the quality of the encoded circuits and show the significant improvements that can be obtained by the synthesis of large controllers.