The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Designing self-timed systems using concurrent programs
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Specification, synthesis, and verification of hazard-free asynchronous circuits
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Verification of asynchronous interface circuits with bounded wire delays
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Self-timed data transmission in massively parallel computing systems
Integrated Computer-Aided Engineering
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Communicating sequential processes
Communications of the ACM
Hazard-Free Asynchronous Circuit Synthesis
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
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This paper introduces an original methodology for hazard-free self-timed design, assuming the worst conditions for robustness. Hazards are classified under three types. Equation hazards are eliminated by an optimal covering. A new variable, labeled state-trajectory is proposed: its integrity guarantees immunity to function hazards. The choice of the delay model for implementation guarantees immunity to logic hazards. Signal-transition graph constraints support safe interaction with synchronous processes. The method was applied to the VLSI CMOS implementation of a router for a parallel machine. Specific cells are designed. Measured performances are presented.