Communicating sequential processes
Communicating sequential processes
Trace theory and systolic computations
Volume I: Parallel architectures on PARLE: Parallel Architectures and Languages Europe
A characterization of ternary simulation of gate networks
IEEE Transactions on Computers
A unified framework for race analysis of asynchronous networks
Journal of the ACM (JACM)
Models and algorithms for race analysis in asynchronous circuits
Models and algorithms for race analysis in asynchronous circuits
Translating programs into delay-insensitive circuits
Translating programs into delay-insensitive circuits
Communications of the ACM
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Recent Developments in the Design of Asynchronous Circuits
FCT '89 Proceedings of the International Conference on Fundamentals of Computation Theory
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Self-timed cellular automata and their computational ability
Future Generation Computer Systems - Cellular automata CA 2000 and ACRI 2000
Testing C-elements is not elementary
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Asynchronous Logic Circuits and Sheaf Obstructions
Electronic Notes in Theoretical Computer Science (ENTCS)
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In classical switching theory, asynchronous sequential circuits are operated in the fundamental mode. In this mode, a circuit is started in a stable state, and then the inputs are changed to cause a transition to another stable state. The inputs are not allowed to change again until the entire circuit has stabilized. In contrast to this, delay-insensitive circuits-the correctness of which is insensitive to delays in their components and wires-use the input-output mode. In this case, it is assumed that inputs may change again, in response to an output change, even before the entire circuit has stabilized. It is shown that such commonly used behaviors as those of the set-reset latch and Muller's C-ELEMENT do not have delay-insensitive realizations, if gates are used as the basic components. It is proved that no nontrivial sequential behavior with one binary input possesses a delay-insensitive realization using gates only. The proof makes use of the equivalence between ternary simulation and the general-multiple-winner model of circuit behavior.