Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Semi-modularity and self-diagnostic asynchronous circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Testing delay-insensitive circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Testability of asynchronous timed control circuits with delay assumptions
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Semi-modularity and testability of speed-independent circuits
Integration, the VLSI Journal - Special issue on high-level synthesis
On the Delay-Sensitivity of Gate Networks
IEEE Transactions on Computers
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
A model for sequential machine testing and diagnosis
Journal of Electronic Testing: Theory and Applications
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
Recent Developments in the Design of Asynchronous Circuits
FCT '89 Proceedings of the International Conference on Fundamentals of Computation Theory
A partial scan methodology for testing self-timed circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Semi-modular Latch Chains for Asynchronous Circuit Design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We examine stuck-at faults in several gate circuits realizing the C-element. We exhibit circuits with the following phenomena: (a) 50% of single faults do not cause the circuit to halt. (b) Some faults are not detectable by logic tests. (c) A test of length seven is required to detect all detectable single faults. (d) A fault may result in an oscillation. (e) A fault may destroy the speed-independence of a circuit. We also analyze static and dynamic CMOS implementations of the C-element.