A communicating Petri net model for the design of concurrent asynchronous modules
DAC '94 Proceedings of the 31st annual Design Automation Conference
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Evaluation of function blocks for asynchronous design
EURO-DAC '94 Proceedings of the conference on European design automation
Externally hazard-free implementations of asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Decomposition and technology mapping of speed-independent circuits using Boolean relations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Detecting Exitory Stuck-At Faults in Semimodular Asynchronous Circuits
IEEE Transactions on Computers
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Delay-insensitive interface specification and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of concurrency to system design
True Concurrency in Models of Asynchronous Circuit Behavior
Formal Methods in System Design
GALA (Globally Asynchronous - Locally Arbitrary) Design
Concurrency and Hardware Design, Advances in Petri Nets
Synthesis of Reactive Systems: Application to Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
Testing C-elements is not elementary
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Optimised state assignment for asynchronous circuit synthesis
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Designing an asynchronous pipeline token ring interface
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Control Resynthesis for Control-Dominated Asynchronous Designs
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Logical timing (global synchronization of asynchronous arrays)
PAS '95 Proceedings of the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
Global Synchronization of Asynchronous Arrays in Logical Time
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Efficient synthesis of speed-independent combinational logic circuits
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Registers for phase difference based logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quasi-delay-insensitive computing device: methodological aspects and practical implementation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of Concurrency to System Design
Design and test of self-checking asynchronous control circuit
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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