Testing delay-insensitive circuits
Testing delay-insensitive circuits
Semi-modularity and testability of speed-independent circuits
Integration, the VLSI Journal - Special issue on high-level synthesis
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Testing asynchronous circuits: a survey
Integration, the VLSI Journal
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
New techniques for synthesis and testing of asynchronous circuits
New techniques for synthesis and testing of asynchronous circuits
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
Design and test of self-checking asynchronous control circuit
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
| Hi-index | 14.98 |
Abstract—Beerel [1] showed that semimodular asynchronous circuits are totally self-checking with respect to multiple output stuck-at faults that are nonexitory and nonsubstitutional. We show that, in circuits with atomic gate implementations, it is possible to ensure that all exitory multiple output stuck-at faults will cause the circuit to halt.