Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Counterflow Pipeline Experiment
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Current Sensor on the Base of Permanent Pre-chargeable Amplifier
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Logical timing (global synchronization of asynchronous arrays)
PAS '95 Proceedings of the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
Global Synchronization of Asynchronous Arrays in Logical Time
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Counterflow Pipeline Processor Architecture
Counterflow Pipeline Processor Architecture
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
From synchronous to GALS: A new architecture for FPGAs
Microelectronics Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The problem of organizing the temporal behavior of digital systems is discussed. This problem is mainly associated with providing the interface between physical (natural) and logical (artificial) time. The most common method of interfacing is based on a system clock that removes physical time from the behavior models A number of algorithms that can be easily formulated in logical time present a great difficulty in the asynchronous case. The suggested GALA (Globally Asynchronous - Locally Arbitrary) design methodology is based on decomposing the system to a Processors Stratum and a Synchro-Stratum. The synchro-stratum acts as a distributed asynchronous clock that produces local synchro-signals for the processor stratum, which is basically a synchronous prototype. A synchro-stratum, like any asynchronous circuit, interacts with the external devices, including the processor stratum, by handshake. Every local device produces an acknowledgment signal and sends it to the synchro-stratum. The designer can use a wide range of methods to implement this signal (Locally Arbitrary): from a self-timed design to a built-in parallel delay. For various disciplines of prototype clocking, corresponding synchro-stratum implementations are suggested. The GALA methodology is illustrated on several design examples, such as a counter with constant response time, one-two-one track FiFo, arbitration-free counterflow processor architecture.