Counterflow Pipeline Processor Architecture

Authors:
Charles E. Molnar;Robert F. Sproull;Ivan E. Sutherland
Affiliations:
-;-;-
Venue:
Counterflow Pipeline Processor Architecture
Year:
1994

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Abstract

The counterflow pipeline processor architecture (CFPP) is aproposal for a family of microarchitectures for RISC processors.The architecture derives its name from its fundamental feature,namely that instructions and results flow in opposite directionswithin a pipeline and interact as they pass. The architecture seeksgeometric regularity in processor chip layout, purely local controlto avoid performance limitations of complex global pipeline stallsignals, and simplicity that might lead to provably correctprocessor designs. Moreover, CFPP designs allow asynchronousimplementations, in contrast to conventional pipeline designs wherethe synchronization required for operand forwarding makesasynchronous designs unattractive. This paper presents the CFPParchitecture and a proposal for an asynchronous implementation.Detailed performance simulations of a complete processor design arenot yet available.