Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
ACM SIGARCH Computer Architecture News
Measurement and evaluation of the MIPS architecture and processor
ACM Transactions on Computer Systems (TOCS)
Communications of the ACM
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
A 100-MIPS GaAs Asynchronous Microprocessor
IEEE Design & Test
A comparision of superscalar and decoupled access/execute architectures
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
PIPE: a VLSI decoupled architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
MC88100 Microprocessors User's Manual
MC88100 Microprocessors User's Manual
Interrupt Handling for Out-of-Order Execution Processors
IEEE Transactions on Computers
Precise exception handling for a self-timed processor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
The architecture and system method of DDM1: A recursively structured Data Driven Machine
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Counterflow Pipeline Processor Architecture
Counterflow Pipeline Processor Architecture
Measuring the Parallelism Available for Very Long Instruction Word Architectures
IEEE Transactions on Computers
An efficient algorithm for exploiting multiple arithmetic units
IBM Journal of Research and Development
Kin: a high performance asynchronous processor architecture
ICS '98 Proceedings of the 12th international conference on Supercomputing
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Computer
Architectural Considerations for Application-Specific Counterflow Pipelines
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
ARCS: an architectural level communication driven simulator
Proceedings of the 14th ACM Great Lakes symposium on VLSI
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Decoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred is a self-timed decoupled, pipelined computer architecture based on micropipelines. We present the architecture of Fred, with specific details on a micropipelined implementation that includes support for multiple functional units and out-of-order instruction completion due to the self-timed decoupling.