Communications of the ACM
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Compiling the language Balsa to delay insensitive hardware
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Communicating sequential processes
Communications of the ACM
CSP Networking for Java (JCSP.net)
ICCS '02 Proceedings of the International Conference on Computational Science-Part II
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Fred: An Architecture for a Self-Timed Decoupled Computer
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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Simulators for digital systems operate at a variety of levels of abstraction varying from detailed analog and switch level modeling of the transistor to cycle based descriptions of entire systems. We propose an even higher level simulator, called ARCS, based on the abstraction of an asynchronous communication event rather than of a clock cycle. Modeling systems at this level allows architectural level exploration of the design space before cycle-level details are available, and also allows the same framework to be used to refine architectural level simulations into more detailed simulations with increasingly fine grained notions of timing. The ARCS simulation framework uses concurrently operating threads in Java with communicating sequential processes (CSP) semantics as a natural expression of communication between concurrent hardware. To avoid synchronization bottlenecks ARCS models time using a communication driven clockwork model which allows for both user configurable runtime viewing of the simulation and post processing of complete simulation timing data.