Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
A 100-MIPS GaAs Asynchronous Microprocessor
IEEE Design & Test
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Fred: An Architecture for a Self-Timed Decoupled Computer
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Design of an Asynchronous Microprocessor
The Design of an Asynchronous Microprocessor
Counterflow Pipeline Processor Architecture
Counterflow Pipeline Processor Architecture
Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware"
Theoretical Computer Science
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
IBM PowerNP network processor: Hardware, software, and applications
IBM Journal of Research and Development
Automatic placement of micropipeline standard cells
WSEAS Transactions on Circuits and Systems
Discrete dynamical genetic programming in XCS
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Design of a low-power embedded processor architecture using asynchronous function units
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
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Virtually all computers today are synchronous, thanks to an internal timing device that regulates processing. As systems grow increasingly large and complex, however, this little device-the clock-can cause big problems with clock skew, a timing delay that can create havoc with the overall design. It can also increase the circuit silicon and power dissipation. In seeking to overcome such limitations, computer architecture researchers are actively considering asynchronous processor design. Asynchronous architectures permit modular design: Each subsystem or functional block can be optimized without being synchronized to a global clock. Moreover, an asynchronous system exhibits the average performance of all components, rather than the worst-case performance of a single component. Asynchronous processors may also reduce power dissipation by inherently shutting down unused portions of the circuit. This article examines the key architecture issues that concern designers and compares six developmental asynchronous architectures. Though asynchronous processors may not match the performance of synchronous processors now, the condition generating the research into asynchronous processors will grow more prevalent as device geometries continue to shrink.