An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
IEEE Transactions on Computers
High-performance computer architecture (2nd ed.)
High-performance computer architecture (2nd ed.)
ACM Computing Surveys (CSUR)
Communications of the ACM - Special issue on computer architecture
The Architecture of Symbolic Computers
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Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
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SCISM: a scalable compound instruction set machine
IBM Journal of Research and Development
IEEE Micro
Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers
HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
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ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Incremental Commit Groups for Non-Atomic Trace Processing
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs)
IEEE Transactions on Computers
iGPU: exception support and speculative execution on GPUs
Proceedings of the 39th Annual International Symposium on Computer Architecture
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Processors with multiple functional units, including the superscalars, achieve significant performance enhancement through low-level execution concurrency. In such processors, multiple instructions are often issued and definitely executed concurrently and out-of-order. Consequently, interrupt and exception handling becomes a vexing problem. The authors identify latency, cost, and performance degradation as factors that must be considered in evaluating the effectiveness of interrupt and exception handling schemes. They then briefly enumerate proposals and implementations for interrupt and exception handling on out-of-order execution processors. An efficient hardware mechanism, the instruction window (IW), and an approach which allows for precise, responsive, and flexible interrupt and exception handling are presented. The implementation of the IW is discussed. The design of an eight-cell IW has been carried out; it can work with a very short machine cycle time. A comparison of all interrupt and exception handling schemes for out-of-order execution processors is also presented.