Communications of the ACM
Scheduling precedence graphs in systems with interprocessor communication times
SIAM Journal on Computing
Scheduling parallel program tasks onto arbitrary target machines
Journal of Parallel and Distributed Computing - Special issue: software tools for parallel programming and visualization
Towards an architecture-independent analysis of parallel algorithms
SIAM Journal on Computing
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Balanced scheduling: instruction scheduling when memory latency is uncertain
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
A comparison of list schedules for parallel processing systems
Communications of the ACM
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
On the Performance Evaluation of Fully Asynchronous Processor Architectures
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Self-Timed Architecture of a Reduced Instruction Set Computer
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Micronets: a model for decentralising control in asynchronous processor architectures
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
ECSTAC: a fast asynchronous microprocessor
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A Comparison of Heuristics for Scheduling DAGs on Multiprocessors
A Comparison of Heuristics for Scheduling DAGs on Multiprocessors
Counterflow Pipeline Processor Architecture
Counterflow Pipeline Processor Architecture
Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing
IEEE Transactions on Computers
NP-complete scheduling problems
Journal of Computer and System Sciences
Paper: Assigning dependency graphs onto processor networks
Parallel Computing
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This paper investigates issues which impinge on the design of static instruction schedulers for micronet-based asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-specific heuristics. Their performance on some program graphs are presented and conclusions are drawn on the suitability of MAP as targets for ILP compilers.