Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Introduction to VLSI Systems
Static Scheduling of Instructions on Micronet-based Asynchronous Processors
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
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This paper introduces some of the principal design issues encountered in the development of a prototype asynchronous microprocessor using a two-phase communication strategy. These issues include the control of the processor pipeline, register tagging, branch techniques, and the implementation of caches. The arbitration and synchronisation methods employed in the design are discussed, and expected performance figures based on block simulation results are given.