Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
Logical timing (global synchronization of asynchronous arrays)
PAS '95 Proceedings of the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
GALA (Globally Asynchronous - Locally Arbitrary) Design
Concurrency and Hardware Design, Advances in Petri Nets
Embedding universal delay-insensitive circuits in asynchronous cellular spaces
Fundamenta Informaticae - Special issue on cellular automata
Embedding Universal Delay-Insensitive Circuits in Asynchronous Cellular Spaces
Fundamenta Informaticae - Cellular Automata
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The problem of global synchronization in massively parallel systems is discussed for the level of models represented by asynchronous cellular automata arrays. Synchronization is called global if a given asynchronous automata array functions in logical time so that its behavior can be homomorphously mapped to the behavior of the prototype synchronous system in physical time. Our approach is decomposing the asynchronous array to synchro-stratum which acts as a distributed asynchronous clock and automata stratum whose automata have a construction similar to that of the synchronous prototype array automata. For various disciplines of prototype synchronization, the corresponding variants of synchro-stratum implementation for the asynchronous analogue are discussed.