Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A FIFO Ring Performance Experiment
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET2e: An Asynchronous Embedded Controller
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A FIFO Data Switch Design Experiment
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Low-Power, Low-Noise, Configurable Self-Timed DSP
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Design Problem SCPP-A
Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region
IEEE Transactions on Computers
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
GALA (Globally Asynchronous - Locally Arbitrary) Design
Concurrency and Hardware Design, Advances in Petri Nets
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
IEEE Transactions on Computers
Hi-index | 0.00 |
The counterflow pipeline architecture [Sproull94] consists of two interacting pipelines in which data items flow in opposite directions. Interactions occur between two items when they meet in a stage. We present the design decisions for, and test measurements from, an asynchronous chip that explores the basic ideas of such an architecture. We built the chip in order to confirm proper operation of the arbiters required to ensure that each and every item flowing in one direction interacts with each and every item flowing in the other direction.Our chip, named ``Zeke,'' was built in 0.6 micron CMOS through the MOSIS fabrication facility. The maximum total throughput of the chip, which is the sum of the throughputs of the two pipelines, varies between 491 MDI/s (Mega Data Items per second) and 699 MDI/s, depending on the amount of interaction that takes place. Under average data and operating conditions the performance of our chip was roughly halfway between these throughput values.