Automatic technology mapping for generalized fundamental-mode asynchronous designs
DAC '93 Proceedings of the 30th international Design Automation Conference
Decomposition methods for library binding of speed-independent asynchronous designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Externally hazard-free implementations of asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A generalized state assignment theory for transformation on signal transition graphs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
General Conditions for the Decomposition of State-Holding Elements
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Structural Methods for the Synthesis of Speed-Independent Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Checking Combinational Equivalence of Speed-Independent Circuits
Formal Methods in System Design
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This paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, e.g., the monotonous cover conditions. We describe an algorithm for the factorization of this circuit aimed at implementing it in a given standard cell library, while preserving speed-independence. The algorithm exploits known efficient factorization techniques from combinational multi-level logic synthesis, but achieves also boolean simplification. Experimental results show a significant improvement in terms of number and complexity of solvable circuits with respect to existing methods.