Automatic synthesis of asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Free choice Petri nets
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Synthesis of speed-independent circuits from STG-unfolding segment
DAC '97 Proceedings of the 34th annual Design Automation Conference
Decomposition and technology mapping of speed-independent circuits using Boolean relations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based on the structural analysis of the underlying Petri net. This methodology can be applied to any STG that can be covered by State Machines and, in particular, to all live and safe free-choice STGs. Significant improvements with regard to existing structural methods are provided. The new techniques have been implemented in an experimental tool that has been able to synthesize specifications with over 1027 markings, some of them being non-free choice.