Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Automatic synthesis of asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Semi-modularity and testability of speed-independent circuits
Integration, the VLSI Journal - Special issue on high-level synthesis
Analysis and identification of speed-independent circuits on an event model
Formal Methods in System Design - Special issue on designing correct circuits
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
On hazard-free implementation of speed-independent circuits
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings
Proceedings of the 7th International Conference on Computer Aided Verification
Hierarchical gate-level verification of speed-independent circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
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We introduce the notion of combinational equivalence to relate two speed-independent asynchronous (sequential) circuits:a “golden” hazard-free circuit C_1 and a “target” circuit C_2 that can be derived from C_1 through only combinational decomposition and extraction. Both circuits are assumed to be networks of single-output basic gates; multiple output gates such as arbiters, toggles, and dual-rail function blocks are not considered. We say that the circuits are combinationally equivalent if the decomposition and extraction preserves the essential functionality of the combinational blocks in the circuit and does not introduce hazards. The paper‘s focus is the bottleneck of the verification procedure, checking whether C_2 is hazard-free. We show that C_2 is hazard-free if and only if all of its signals are monotonic and acknowledged. We then show how cubes that approximate sets of reachable circuit states can be used to give sufficient conditions for monotonicity and acknowledgement. These sufficient conditions are used to develop a verification technique for combinational equivalence that can be exponentially faster than applying traditional, more general verification techniques. This result can be useful for verifying logic synthesis and technology mapping procedures.