Selected papers of the Second Workshop on Concurrency and compositionality
A generalized state assignment theory for transformations on signal transition graphs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
On the verification of state-coding in STGs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
A generalized state assignment theory for transformations on signal transition graphs
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Synthesizing Petri nets from state-based models
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Efficient state assignment framework for asynchronous state graphs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A Fundamental Tehoerem of Asynchronous Parallel Computation
Proceedings of the Sagamore Computer Conference on Parallel Processing
Petri Net Analysis Using Boolean Manipulation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
Optimised state assignment for asynchronous circuit synthesis
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Checking signal transition graph implementability by symbolic BDD traversal
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Formal method for self-timed design
EURO-DAC '91 Proceedings of the conference on European design automation
Asynchronous circuit synthesis with Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decomposition and technology mapping of speed-independent circuits using Boolean relations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Deriving Petri Nets from Finite Transition Systems
IEEE Transactions on Computers
Logic Synthesis and Verification
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
From STG to Extended-Burst-Mode Machines
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal verification of synchronizers
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
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Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which happens when a pair of different states in an SG has the same binary encoding. A standard way to approach state coding conflicts is to add new state signals into the original specification in such a way that the original behaviour remains intact. Existing methods have not yet been able to provide such theoretical foundation for event insertion, that could yield efficient practical results when applied to large models.This paper aims at presenting such a general framework, which is based on two fundamental concepts. One is a region of states in an abstract labeled SG (called a Transition System). Regions correspond to places in the associated STG. The second concept is a speed-independence preserving set, which is strongly related to the implementability of the model in logic. Regions and their intersections offer ``nice'' structural properties that make them efficient ``construction blocks'' for event insertion. The application of our theory, through the software tool petrify, to state graphs of large size has proved to be successful.