On the models for designing VLSI asynchronous digital systems
Integration, the VLSI Journal
Specification and verification of asynchronous circuits using marked graphs
Concurrency and nets: advances in Petri nets
Solving the state assignment problem for signal transition graphs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
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Formal method of self-timed circuit design, based on compact event model - change diagrams (CD), is suggested. This model (CD) seems to be very attractive because of convenient tools for describing the semantics of concurrency which allows to enhance the specification from distributive class of processes to semimodular ones. The necessary and sufficient conditions of CD correctness and polynomial algorithms of their analysis are introduced. The formal synthesis procedure consider as the set of equivalent transformations of initial specification (inserting to it the additional signals) that exclude some incorrectnesses (contradiction, abnormality and so on). The boolean equations of implementing self-timed circuit can be easily obtained from the corrected description.