Communicating sequential processes
Communicating sequential processes
Petr nets, algebras, morphisms, and compositionality
Information and Computation
Translating programs into delay-insensitive circuits
Translating programs into delay-insensitive circuits
SHILPA: a high-level synthesis system for self-timed circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
A communicating Petri net model for the design of concurrent asynchronous modules
DAC '94 Proceedings of the 31st annual Design Automation Conference
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
A general state graph transformation framework for asynchronous synthesis
EURO-DAC '94 Proceedings of the conference on European design automation
Synthesizing Petri nets from state-based models
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Peephole Optimization of Asynchronous Macromodule Networks
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
An Algebra for Delay-Insensitive Circuits
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Deriving Petri Nets from Finite Transition Systems
IEEE Transactions on Computers
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems
Proceedings of the 39th annual Design Automation Conference
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of concurrency to system design
Is the Die Cast for the Token Game?
ICATPN '02 Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets
A Timing Verifier and Timing Profiler for Asynchronous Circuits
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Logic Synthesis of Handshake Components Using Structural Clustering Techniques
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of Concurrency to System Design
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This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic components previously implemented by skilled designers. However, the generality of the approach often involves the insertion of redundant functionality to the circuit.We propose a new approach based on the composition of Petri nets and the automatic synthesis through Signal Transition Graphs that allows to take advantage of logic synthesis methods to optimize the circuit and make it portable for different delay models and technologies. Some preliminary experimental results have shown the effectiveness of the approach to improve the quality of the circuits.