A design and validation system for asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing verification for asynchronous design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A System for Asynchronous High-speed Chip to Chip Communication
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
An Asynchronous PRBS Error Checker for Testing High-Speed Self-Clocked Serial Links
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automatic placement of micropipeline standard cells
WSEAS Transactions on Circuits and Systems
| Hi-index | 0.00 |
A system for timing verification and timing profiling of asynchronous circuits is presented. A hierarchical netlist is simulated with an ordinary simulator such as HSPICE. Signal transition information is extracted from the simulation results. The system uses this information and the netlist to compare the circuit to Generalized Signal Transition Graph specifications by simulating the flow of tokens in the graphs. If a signal makes a transition that is not allowed by the specification, a timing error has occurred. The flow of tokens in the graph is also used to produce timing statistics for the circuit. Based on these statistics, timing optimization can be done in an iterative design process.