Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Stari: a technique for high-bandwidth communication
Stari: a technique for high-bandwidth communication
SCI-LVDS 500 MHz differential pad drivers in a standard CMOS process
Analog Integrated Circuits and Signal Processing
Design of Self-timed Multipliers: A Comparison
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
A Timing Verifier and Timing Profiler for Asynchronous Circuits
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A High-Speed Clockless Serial Link Transceiver
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
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A system for high-speed asynchronous interconnections between VLSI chips is proposed. Communication is performed on three-wire links that have about the same properties as differential interconnections. A bit transmission consists of switching the constant driver current from one wire to one of the two others. There is no need for clocking or synchronisation, as bits are separated by a transition. The chosen data representation makes decoding to a two-phase protocol especially simple. Energy consumption may be reduced by dynamically adjusting bias currents, and thus circuit speed, to match the demand for communication bandwidth. In a 0.7\mu m CMOS process, communication bandwidth per link is expected to reach 1Gb/s.