Distributed mutual exclusion on a ring of processes
Science of Computer Programming
Formal program transformations for VLSI circuit synthesis
Formal development programs and proofs
Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Communicating sequential processes
Communications of the ACM
A System for Asynchronous High-speed Chip to Chip Communication
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Performance Electrical Signaling
MPPOI '98 Proceedings of the The Fifth International Conference on Massively Parallel Processing Using Optical Interconnections
Wave-pipelined on-chip global interconnect
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
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We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high off-chip data rates by using multiplexing transmitters and demultiplexing receivers that interface parallel on-chip data paths with high-speed, serial off-chip buses. While synchronous transceivers commonly use multi-phase clocks to control the data multiplexing and demultiplexing, our clockless transceiver uses a token-ring architecture that eliminates complex clock generation and synchronization circuitry. Furthermore, our clockless receiver dynamically self-adjusts its sampling rate to match the bit rate of the transmitter. Our SPICE simulations report that in a 0.18-µm CMOS technology this transceiver design operates at up to 3-Gb/s and dissipates 77 mW of power with a 1.8-V supply voltage.