Communicating sequential processes
Communicating sequential processes
Modeling concurrency with partial orders
International Journal of Parallel Programming
A formal semantics for concurrent systems with a priority relation
Acta Informatica
Temporal logic and causality in concurrent systems
International Conference on Concurrency on Concurrency 88
Translating programs into delay-insensitive circuits
Translating programs into delay-insensitive circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
A partial ordering semantics for CCS
Theoretical Computer Science
Distributed computing: models and methods
Handbook of theoretical computer science (vol. B)
Petri net semantics of priority systems
Selected papers of the Second Workshop on Concurrency and compositionality
A unified signal transition graph model for asynchronous control circuit synthesis
Formal Methods in System Design
Delay-Insensitivity and Semi-Modularity
Formal Methods in System Design
Delay-insensitivity and ternary simulation
Theoretical Computer Science
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
Invariants and Paradigms of Concurrency Theory
PARLE '91 Proceedings of Parallel Architectures and Languages - Volume II
Invariant Semantics of Nets with Inhibitor Arcs
CONCUR '91 Proceedings of the 2nd International Conference on Concurrency Theory
The Observation Algebra of Spatial Pomsets
CONCUR '91 Proceedings of the 2nd International Conference on Concurrency Theory
Truly Concurrent Constraint Programming
CONCUR '96 Proceedings of the 7th International Conference on Concurrency Theory
Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Partial-Order Model Checking: A Guide for the Perplexed
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Semantic quality attributes for big-step modelling languages
FASE'11/ETAPS'11 Proceedings of the 14th international conference on Fundamental approaches to software engineering: part of the joint European conferences on theory and practice of software
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In the study of asynchronous designs most authors use the interleaving model of concurrency when describing the behavior of a network; this is usually done for simplicity. The interleaving model assumes the behavior of an asynchronous circuit can be adequately represented by allowing only one signal to change at a time. In contrast to this, true concurrency models allow an arbitrary number of simultaneous signal changes. It seems that little effort has been made to determine what effect the choice of model may have on the analysis of a network. In this paper, we attempt to discover the circumstances under which the assumption of single signal changes can be made without affecting the results of circuit analysis. We prove, in a formal network model, that, in the context of delay-insensitivity and semi-modularity, the single change assumption is valid. We also prove that the same is true for a different definition of delay-insensitivity, restricted to deterministic behaviors. Consequently, in these cases, the more complicated true concurrency analysis is not required.