An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
On the Delay-Sensitivity of Gate Networks
IEEE Transactions on Computers
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
Testing C-elements is not elementary
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
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