GRIP—A high-performance architecture for parallel graph reduction
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FCT '89 Proceedings of the International Conference on Fundamentals of Computation Theory
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A Futurebus interface design using standard parts as part of the GRIP (Graph Reduction in Parallel) project is described. The GRIP system and the IEEE P896 Futurebus standard are examined. The implementation, which is unusual in its use of fully synchronous finite-state machines, is then presented. A diagnostics board that interfaces directly to a Unix host computer is described. Some lessons for designers using Futurebus are drawn from the experience.