Communicating sequential processes
Communicating sequential processes
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Avoiding the state explosion problem in temporal logic model checking
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Integration, the VLSI Journal
On the Delay-Sensitivity of Gate Networks
IEEE Transactions on Computers
TABLEAUX '96 Proceedings of the 5th International Workshop on Theorem Proving with Analytic Tableaux and Related Methods
Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language
Proceedings of the 12th European Simulation Multiconference on Simulation - Past, Present and Future
The Design of an Asynchronous Microprocessor
The Design of an Asynchronous Microprocessor
Limitations to Delay-Insensitivity in Asynchronous Circuits
Limitations to Delay-Insensitivity in Asynchronous Circuits
Compiling Communicating Processes into Delay-Insensitive VLSI Circuits
Compiling Communicating Processes into Delay-Insensitive VLSI Circuits
Induced hierarchical verification of asynchronous circuits using a partial order technique
Induced hierarchical verification of asynchronous circuits using a partial order technique
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
IEEE Transactions on Computers
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Simulation of large asynchronous logic circuits using an ambiguous gate model
AFIPS '71 (Fall) Proceedings of the November 16-18, 1971, fall joint computer conference
An analysis of parallel synchronous and conservative asynchronous logic simulation schemes
SPDP '94 Proceedings of the 1994 6th IEEE Symposium on Parallel and Distributed Processing
| Hi-index | 0.00 |
This article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a ''bridge'' between static logic analysis and detailed simulation.