Modeling concurrency with partial orders
International Journal of Parallel Programming
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
Syntax-directed translation of concurrent programs into self-timed circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Partial-Order Model Checking: A Guide for the Perplexed
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of Concurrency to System Design
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A syntax-directed translation procedure for the synthesis of delay-insensitive circuits from graph-theoretic specifications is presented. No isochronic fork assumption is required for the correct operation of the synthesized circuits. The synthesized circuits are different from those obtained from Ebergen's synthesis method [6]. In Ebergen's circuits, the voltage levels of a set of wires are used to encode which input events are most recently received. Special circuit elements (the N-element or the RCEL element) and two-phase to four-phase converters are needed to change the voltage levels of the encoding wires when input events are received. In the circuits obtained from the method in this paper, the wires encoding which input events are most recently received are the outputs of the toggles. When input events are received, they are sent directly or via demuitiplexers to the toggles to change the voltage levels at their outputs. Two-phase to four-phase converters are not needed. The synthesis method is compared with Ebergen's synthesis method.