Power Aware Design Methodologies
Power Aware Design Methodologies
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Computing synchronizer failure probabilities
Proceedings of the conference on Design, automation and test in Europe
Nanometer CMOS ICs: from Basics to ASICs
Nanometer CMOS ICs: from Basics to ASICs
Adapting Synchronizers to the Effects of on Chip Variability
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
A voltage-frequency island aware energy optimization framework for networks-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Synchronizer Behavior and Analysis
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Synchronization and Arbitration in Digital Systems
Synchronization and Arbitration in Digital Systems
Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer
ASYNC '10 Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
Extending Synchronization from Super-Threshold to Sub-threshold Region
ASYNC '10 Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
The Devolution of Synchronizers
ASYNC '10 Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
Understanding dc behavior of subthreshold CMOS logic through closed-form analysis
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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Sub-threshold operation has been proven to be very effective to reduce the power consumption of circuits when high performance is not required. Future low power systems on chip are likely to consist of many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold region. Synchronizers are therefore needed to interface between these sub-systems. However, VDD scaling rapidly degrades synchronizers' performance making them unsuitable for sub-threshold operation. For the first time, we analyze the synchronizer performance at ultra low voltages and propose to apply forward body bias to extend the operation of synchronizers to the sub-threshold region and to make them resilient to process variation. We show that applying full-VDD bias significantly increases the transconductance of the bi-stable in synchronizers without adding capacitance to the switching nodes. As a result all the circuit parameters (@t metastability time constant, T"d normal propagation delay and T"w metastability window) determining synchronizer performance or mean time between failure (MTBF) can be improved by more than 80% (i.e. by five times) in the sub-threshold region. We also study the impact of process variation on the synchronizer performance in the sub-threshold region and conclude that with full-VDD bias the synchronizer MTBF can be improved from seconds to years for the worst case corner. Finally, we propose an implementation scheme of full-VDD body-biased synchronizer, which is able to work for a wide range of VDDs from sub-threshold region to nominal VDD with nearly zero overhead.