Analysis and Design of Integrated Circuits
Analysis and Design of Integrated Circuits
Energy Considerations in Multichip-Module Based Multiprocessors
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Improving power-delay performance of ultra-law-power subthreshold SCL circuits
IEEE Transactions on Circuits and Systems II: Express Briefs
Microelectronics Journal
A 36μW heartbeat-detection processor for a wireless sensor node
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library
Proceedings of the 48th Design Automation Conference
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates
Proceedings of the 48th Design Automation Conference
| Hi-index | 0.00 |
In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the pn-ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.