Improving power-delay performance of ultra-law-power subthreshold SCL circuits

Authors:
Armin Tajalli;Massimo Alioto;Yusuf Leblebici
Affiliations:
Microelectronic Systems Laboratory, Swiss Federal Institute of Technology, Lausanne, Switzerland;Information Engineering Department, University of Siena, Siena, Italy;Microelectronic Systems Laboratory, Swiss Federal Institute of Technology, Lausanne, Switzerland
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

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Abstract

This brief presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. Based on the proposed approach, a source-follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18-µm CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing subthreshold ultra-low power SCL logic gates with a better power and area efficiency, compared to the traditional SCL subthreshold circuits. An optimized approach is proposed to improve the power efficiency of ultra-low power STSCL library cells.