Robust Design of High Fan-In/Out Subthreshold Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Proceedings of the 13th international symposium on Low power electronics and design
Understanding dc behavior of subthreshold CMOS logic through closed-form analysis
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Designing ultra-low voltage logic
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.