Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Utilizing reverse short channel effect for optimal subthreshold circuit design
Proceedings of the 2006 international symposium on Low power electronics and design
New subthreshold concepts in 65nm CMOS technology
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Understanding dc behavior of subthreshold CMOS logic through closed-form analysis
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A fine-grained many VT design methodology for ultra low voltage operations
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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We have investigated the impact of inverse narrow width effect on the threshold voltage and drain current in the near/sub-threshold region at three technology nodes (90 nm, 65 nm and 40 nm) and proposed a new sub-threshold device sizing method which is inverse-narrow-width-effect-aware to reduce the gate area, power consumption and delay. We applied the proposed sizing method in designing a 40 nm sub-threshold standard cell library. Compared with the sub-threshold standard cell library designed using the conventional sizing method, the proposed library has up to 20% less delay, up to 34% less power consumption and up to 47% less area. We used the proposed library for designing a digital base-band processor and achieved a total power consumption of around 5 μw with 6 MHz at 0.5 V, which is 17% better than the counterpart design.