An asynchronous low-power high-performance sequential decoder implemented with QDI templates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-resetting latches for asynchronous micro-pipelines
Proceedings of the 44th annual Design Automation Conference
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-linear asynchronous micro-pipelines
Proceedings of the 12th International Conference on Computer Systems and Technologies
Hi-index | 0.00 |
Many approaches recently proposed for high-speed asynchronouspipelines are applicable only to linear datapaths. However,real systems typically have non-linearities in their datapaths, i.e.stages may have multiple inputs ("joins") or multiple outputs("forks"). This paper presents several new pipeline templatesthat extend existing high-speed approaches for linear dynamiclogic pipelines, by providing efficient control structures that canaccommodate forks and joins. In addition, constructs forconditional computation are also introduced. Timing analysisand SPICE simulations show that the performance overhead ofthese extensions is fairly low (5% to 20%).