An asynchronous matrix-vector multiplier for discrete cosine transform

Authors:
Kyeounsoo Kim;Peter A. Beerel;Youpyo Hong
Affiliations:
Ilryung Telesys, Inc., 7F, Hanmi Bldg., Sungnae3-dong, Kangdong-gu, Seoul 134-033, Korea;EE-Systems Dept., USC, 3740 McClintock Avenue, Los Angeles, CA;Electronic Engr. Dept., Dongguk Univ., 26, 3-Ga, Pil-dong, Jung-gu, Seoul 100-715, Korea
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

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Abstract

This paper proposes an efficient asynchronous hardwired matrix-vector multiplier for the rwo-dimensional discrete cosine transform and inverse discrete cosine transform (DCT/IDCT). The design achieves low power and high performance by taking advantage of the typically large fraction of zero and small-valued data in DCT and IDCT applications. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit-partitioned adders using simplified, static-logic-based speculative completion sensing. The results extracted by both bit-level analysis and HSPICE simulations indicate significant improvements compared to traditional designs.