DAC '98 Proceedings of the 35th annual Design Automation Conference
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
A compact physical via blockage model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Multiobjective optimization of VLSI interconnect parameters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Toward accurate models of achievable routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Investigation of performance metrics for interconnect stack architectures
Proceedings of the 2004 international workshop on System level interconnect prediction
Power consumption of fault tolerant busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given interconnect architecture (IA). This new metric, the rank of an IA, is a single number that gives the number of connections in the WLD that meet a specific target delay when embedded in the IA. A dynamic programming algorithm is presented to exactly compute the rank of an IA with respect to a given WLD within practical runtimes. We use our new IA metric to quantitatively compare impacts of geometric parameters as well as process and material technology advances. For example, we observe that 42% reduction in Miller coupling factor achieves the same rank improvement as a 38% reduction in inter-layer dielectric permittivity for a 1M gate design in the 130nm technology.