A compact physical via blockage model

Authors:
Qiang Chen;Jeffrey A. Davis;Payman Zarkesh-Ha;James D. Meindl
Affiliations:
Georgia Institute of Technology, Atlanta;Georgia Institute of Technology, Atlanta;Georgia Institute of Technology, Atlanta;Georgia Institute of Technology, Atlanta
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Year:
2000

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Abstract

Via blockage due to signal interconnects and its impact on wirability of multi-billion-transistor chips are systematically analyzed. Via classifications are introduced. By taking advantage of a stochastic interconnect length distribution and a multi-level interconnect network architecture, a physical via blockage model exploiting channel availability is proposed. This model reveals that the most severe via blockage occurs on first metal level, wasting more than 10% and up to about 50% of wiring area. A new perspective on chip size limit imposed by via blockage is also provided by using the proposed model.